The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Aug. 10, 2020
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Akihiro Hikasa, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/07 (2006.01); H01L 29/739 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0716 (2013.01); H01L 29/0619 (2013.01); H01L 29/0692 (2013.01); H01L 29/0696 (2013.01); H01L 29/0804 (2013.01); H01L 29/1095 (2013.01); H01L 29/41708 (2013.01); H01L 29/4236 (2013.01); H01L 29/7397 (2013.01); H01L 29/7841 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01);
Abstract

A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an nemitter region and an ndrain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the nemitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.


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