The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2023
Filed:
Jun. 16, 2020
Applicant:
Infineon Technologies Llc, San Jose, CA (US);
Inventors:
Krishnaswamy Ramkumar, San Jose, CA (US);
Venkatraman Prabhakar, Pleasanton, CA (US);
Assignee:
Infineon Technologies LLC, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/8238 (2006.01); H01L 27/11563 (2017.01); H01L 27/092 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01); H01L 27/11563 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract
Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor. The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.