The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Aug. 03, 2021
Applicant:

Jadard Technology Inc., Shenzhen, CN;

Inventors:

Feng-Wei Lin, Tainan, TW;

Yu-Chieh Hsu, Tainan, TW;

Hong-Yun Wei, Shenzhen, CN;

Assignee:

JADARD TECHNOLOGY INC., Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 27/02 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
G11C 27/02 (2013.01); H03M 1/1245 (2013.01);
Abstract

A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.


Find Patent Forward Citations

Loading…