The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Nov. 18, 2021
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Isao Houda, Tokyo, JP;

Aya Ohmae, Tokyo, JP;

Umberto Paoletti, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/309 (2006.01); H05K 1/02 (2006.01); G01R 1/067 (2006.01);
U.S. Cl.
CPC ...
G01R 31/309 (2013.01); G01R 1/06711 (2013.01); H05K 1/0216 (2013.01);
Abstract

Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe. The IC reaching signal level estimation unit reads the coupling characteristics from the storage unit based on the board design information of a test subject circuit board and the information of the near-field probe, and outputs a value of the IC reaching signal level reaching a terminal of the evaluation target IC from the board design information of the test subject circuit board, the information of the near-field probe, and the coupling characteristics.


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