The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Jun. 24, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Stephan Pindl, Ergoldsbach, DE;

Carsten Ahrens, Regensburg, DE;

Stefan Jost, Munich, DE;

Ulrich Krumbein, Rosenheim, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 3/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00658 (2013.01); B81B 3/007 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0127 (2013.01); B81C 2201/016 (2013.01); B81C 2201/0125 (2013.01); B81C 2201/0133 (2013.01); B81C 2201/0143 (2013.01); B81C 2201/053 (2013.01); B81C 2203/03 (2013.01);
Abstract

A method for providing a semiconductor layer arrangement on a substrate which comprises providing a semiconductor layer arrangement having a functional layer and a semiconductor substrate layer, attaching the semiconductor layer arrangement to a glass substrate layer such that the functional layer is arranged between the glass substrate layer and the semiconductor substrate layer, and removing the semiconductor substrate layer at least partially such that the glass substrate layer substitutes the semiconductor substrate layer as the substrate of the semiconductor layer arrangement.


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