The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Dec. 14, 2020
Applicant:

Mellanox Technologies, Ltd., Yokneam, IL;

Inventors:

Dotan David Levi, Kiryat Motzkin, IL;

Avraham Ganor, Shoham, IL;

Arnon Sattinger, Zichron Yaakov, IL;

Natan Manevich, Ramat Hasharon, IL;

Reuven Kogan, Yokneam Ilit, IL;

Artiom Tsur, Afula, IL;

Ariel Almog, Kohav Yair, IL;

Bar Shapira, Tel-Aviv, IL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 67/1095 (2022.01); G06F 1/12 (2006.01); G06F 1/14 (2006.01);
U.S. Cl.
CPC ...
H04L 67/1095 (2013.01); G06F 1/12 (2013.01); G06F 1/14 (2013.01);
Abstract

A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.


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