The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Oct. 25, 2021
Applicant:

Ess Technology, Inc., San Jose, CA (US);

Inventors:

Yongsheng Xu, Kelowna, CA;

Dustin Dale Forman, Kelowna, CA;

Assignee:

ESS Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03M 1/18 (2006.01); H03M 7/34 (2006.01); H03M 1/06 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/183 (2013.01); H03M 1/0626 (2013.01); H03M 3/30 (2013.01); H03M 7/3051 (2013.01);
Abstract

Described herein is an apparatus and method for enhancing the dynamic range of an analog-to-digital converter (ADC). In one embodiment of the present approach, an analog input signal is amplified in a programmable gain amplifier (PGA) before the ADC receives the signal, so that the gain applied to an input signal, and gain (or attenuation) later applied in order to balance the overall gain of the circuit, occurs only in either the analog domain; in the prior art, gain occurs partly in each domain. The ADC gain is then adjusted to compensate for gain of the PGA and balance the overall gain of the circuit. In another embodiment, the ADC gain is adjusted, and gain of a digital gain element that receives the signal from the ADC is adjusted to compensate for the ADC gain and balance the overall gain of the circuit, eliminating the need for a PGA.


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