The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Jan. 31, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hector Ivan Oporta, Scotts Valley, CA (US);

Daragh MacGabhann, Raleigh, NC (US);

Chunping Song, Palo Alto, CA (US);

Yi Wang, Cupertino, CA (US);

Ji Hoon Hyun, San Jose, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H03K 19/0185 (2006.01); H03K 17/0412 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); H03K 17/04123 (2013.01); H03K 19/018521 (2013.01); H03K 2217/0081 (2013.01);
Abstract

Power supply circuit having low quiescent current for a bypass mode. One example power supply circuit generally includes a transistor; a switching node coupled to a source of the transistor; a power supply rail; a capacitor having a first terminal coupled to the power supply rail and having a second terminal coupled to the switching node; a gate driver having an output coupled to a gate of the transistor, having a first power input coupled to the power supply rail, and having a second power input coupled to the switching node; logic having a first input coupled to the first terminal of the capacitor, having a second input coupled to the second terminal of the capacitor, and having a first output; and a pullup circuit having a control input coupled to a second output of the logic and having an output coupled to the gate of the transistor.


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