The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Nov. 15, 2021
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Tseng-Fu Lu, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 29/401 (2013.01); H01L 29/4916 (2013.01); H01L 29/518 (2013.01); H01L 29/66621 (2013.01); H01L 29/78 (2013.01); H01L 27/108 (2013.01);
Abstract

The present disclosure provides a method for preparing a semiconductor structure. The method includes providing a substrate comprising a first top surface; forming an isolation region in the substrate to surround an active region; implanting a plurality of dopants into the substrate to form a first impurity region, a second impurity region and a third impurity region in the active region; forming a gate trench in the active region; forming a first barrier layer on a portion of a sidewall of the gate trench; forming a first gate material in the gate trench, wherein the first gate material comprises a first member surrounded by the first barrier layer; forming a second barrier layer on the first barrier layer and the first gate material; forming a second gate material on the second barrier layer; and forming a gate insulating material on the second gate material.


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