The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2023
Filed:
Apr. 27, 2020
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
John Paul Lesso, Edinburgh, GB;
John Laurence Pennock, Edinburgh, GB;
Cirrus Logic, Inc., Austin, TX (US);
Abstract
This application relates to computing circuitry (), in particular for analogue computing circuitry suitable for neuromorphic computing. The circuitry () has a plurality of memory cells (), each memory cell having an input electrode () for receiving a cell input signal and an output () for outputting a cell output signal (I, I), with first and second paths connecting the input electrode to the output. The cell output signal thus depends on a differential current between the first and second paths due to the cell input signal. Each memory cell also comprises at least one programmable-resistance memory element () in each of the first and second paths and is controllable, by selective programming of the programmable-resistance memory elements, to store a data digit that can take any of at least three different values. The plurality of memory cells are configured into one or more sets () of memory cells and a combiner module () receives the cell output signals from each of the memory cells in at least one set, and combines the cell output signals with a different scaling factor applied to each of the cell output signals.