The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Jun. 28, 2019
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Amol A Ambardekar, Redmond, WA (US);

Boris Bobrov, Kirkland, WA (US);

Kent D. Cedola, Bellevue, WA (US);

Chad Balling McBride, North Bend, WA (US);

George Petre, Redmond, WA (US);

Larry Marvin Wall, Seattle, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/499 (2006.01); G06F 7/523 (2006.01); G06F 7/57 (2006.01); G06F 9/30 (2018.01); G06N 3/063 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 7/49994 (2013.01); G06F 7/523 (2013.01); G06F 7/57 (2013.01); G06F 9/30029 (2013.01);
Abstract

Neural processing elements are configured with a hardware AND gate configured to perform a logical AND operation between a sign extend signal and a most significant bit ('MSB') of an operand. The state of the sign extend signal can be based upon a type of a layer of a deep neural network ('DNN') that generate the operand. If the sign extend signal is logical FALSE, no sign extension is performed. If the sign extend signal is logical TRUE, a concatenator concatenates the output of the hardware AND gate and the operand, thereby extending the operand from an N-bit unsigned binary value to an N+1 bit signed binary value. The neural processing element can also include another hardware AND gate and another concatenator for processing another operand similarly. The outputs of the concatenators for both operands are provided to a hardware binary multiplier.


Find Patent Forward Citations

Loading…