The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2023
Filed:
Apr. 15, 2019
Vayo (Shanghai) Technology Co., Ltd., Shanghai, CN;
Shengjie Qian, Shanghai, CN;
Fengshou Liu, Shanghai, CN;
VAYO (SHANGHAI) TECHNOLOGY CO., LTD., Shanghai, CN;
Abstract
A method for detecting an open/short circuit on a PCB design layout includes: reading PCB data of a to-be-checked PCB design layout, to output an image of each PCB layer included in the PCB design layout; performing a first connectivity analysis on the image of each PCB layer to classify pad patterns connected with each other in the same layer into a corresponding child network group; performing a second connectivity analysis to classify child network groups in which pad patterns connected by the same electroplated hole, into a corresponding parent network group; reading IPC netlist data of the PCB design layout, to obtain a netlist network group in which each pad pattern is; and determining whether a netlist network relationship of the pad patterns is consistent with a network relationship obtained after the second connectivity analysis in order to determine whether there is an open/short circuit.