The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Jan. 13, 2020
Applicant:

Gsi Technology Inc., Sunnyvale, CA (US);

Inventors:

LeeLean Shu, Los Altos, CA (US);

Avidan Akerib, Tei Aviv, IL;

Assignee:

GSI Technology Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/11 (2006.01); G06F 7/48 (2006.01); G06F 7/501 (2006.01); G06F 7/506 (2006.01);
U.S. Cl.
CPC ...
G06F 17/11 (2013.01); G06F 7/4824 (2013.01); G06F 7/501 (2013.01); G06F 7/506 (2013.01);
Abstract

A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit. The full adder unit does not overwrite any of the bits when a full adder table indicates that the sum bit and the carry out bit are equivalent to the second bit and the carry-in bit.


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