The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

May. 25, 2017
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Dmitri Yudanov, Austin, TX (US);

Michael Ignatowski, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 29/02 (2006.01); G11C 29/30 (2006.01); G11C 29/44 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 5/14 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 13/1668 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 5/147 (2013.01); G11C 7/06 (2013.01); G11C 29/30 (2013.01); G11C 29/44 (2013.01); G11C 7/1012 (2013.01); G11C 29/025 (2013.01);
Abstract

A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.


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