The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Dec. 29, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Bharat Kumar Rangarajan, Bangalore, IN;

Rajesh Arimilli, Bangalore, IN;

Rengarajan Ragavan, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3237 (2019.01); G06F 21/74 (2013.01); G06F 3/06 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3237 (2013.01); G06F 3/0622 (2013.01); G06F 3/0625 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 21/74 (2013.01); G06F 15/7807 (2013.01);
Abstract

Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.


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