The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Oct. 13, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Roswald Francis, Kildare, IE;

Edward Cullen, Kildare, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03H 11/04 (2006.01); H02M 3/155 (2006.01); G05F 1/46 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G05F 1/46 (2013.01); H02M 3/155 (2013.01); H03H 11/04 (2013.01);
Abstract

Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power supply circuit. The feedback circuit may be configured to sense the second power supply voltage, to process the sensed second power supply voltage, and to output at least one feedback signal to control the first power supply circuit based on the processed second power supply voltage. The clock distribution network may include first and second sets of clock drivers powered by the first and second power supply voltages, respectively.


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