The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Oct. 12, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Akira Tanabe, Tokyo, JP;

Kazuya Uejima, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); G05F 1/44 (2006.01); G01R 31/40 (2020.01); H01L 27/092 (2006.01); G04C 10/02 (2006.01); H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
G05F 1/44 (2013.01); G01R 31/40 (2013.01); G04C 10/02 (2013.01); H01L 27/092 (2013.01); H03K 17/00 (2013.01);
Abstract

An electronic system device comprises a power generation device generating a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitor circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage and supplies charges based on the substrate bias voltage to the capacitor while the switch is ON-state. While the switch is OFF-state, the capacitor stores the accumulated charges based on the substrate bias voltage. While the switch is ON-state, the substrate bias generation circuit adds based on the substrate bias voltage to charge that was held, and states the back bias voltage. The substrate bias generation circuit supplies the back bias voltage to memory circuit.


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