The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Feb. 05, 2021
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Hiroaki Tokuya, Kyoto, JP;

Hideyuki Sato, Kyoto, JP;

Fumio Harima, Kyoto, JP;

Kenichi Shimamoto, Kyoto, JP;

Satoshi Tanaka, Kyoto, JP;

Takayuki Kawano, Kyoto, JP;

Ryoki Shikishima, Kyoto, JP;

Atsushi Kurokawa, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/30 (2006.01); H03F 3/24 (2006.01); H01L 23/00 (2006.01); H03F 3/195 (2006.01);
U.S. Cl.
CPC ...
H03F 3/245 (2013.01); H01L 24/14 (2013.01); H03F 1/302 (2013.01); H03F 3/195 (2013.01); H01L 2224/1403 (2013.01); H03F 2200/451 (2013.01);
Abstract

A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.


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