The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Dec. 12, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Joerg Erik Goller, Tiefenbach, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/157 (2006.01); H02M 3/156 (2006.01); G06F 7/58 (2006.01); H02M 1/44 (2007.01); G01R 31/3183 (2006.01); H02M 1/08 (2006.01);
U.S. Cl.
CPC ...
H02M 3/157 (2013.01); G06F 7/584 (2013.01); H02M 1/44 (2013.01); H02M 3/156 (2013.01); G01R 31/318385 (2013.01); H02M 1/082 (2013.01);
Abstract

An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.


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