The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Jan. 08, 2021
Applicant:

Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;

Inventors:

Mustafa Pinarbasi, Morgan Hill, CA (US);

Andrew J. Walker, Mountain View, CA (US);

Dafna Beery, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
H01L 43/08 (2013.01); G11C 11/161 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H01L 27/228 (2013.01); H01L 43/02 (2013.01); H01L 43/10 (2013.01);
Abstract

A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin orbit torque switching while also consuming a small amount of wafer real estate. The vertical transistor structure can include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure such that the gate dielectric layer separates the gate structure from the semiconductor pillar.


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