The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Aug. 11, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sasikanth Manipatruni, Hillsboro, OR (US);

Dmitri E. Nikonov, Beaverton, OR (US);

Ian A. Young, Portland, OR (US);

Assignee:

INTEL CORPORATON, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01L 43/10 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/224 (2013.01); H01L 43/02 (2013.01); H01L 43/10 (2013.01); H01L 43/12 (2013.01);
Abstract

A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.


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