The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Mar. 26, 2021
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Douglas Carlson, Lowell, MA (US);

Timothy E. Boles, Tyngsboro, MA (US);

Wayne Mack Struble, Franklin, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 21/8258 (2006.01); H01L 23/66 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/76224 (2013.01); H01L 21/8258 (2013.01); H01L 23/66 (2013.01); H01L 27/0605 (2013.01); H01L 2223/6672 (2013.01); H01L 2223/6683 (2013.01);
Abstract

Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.


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