The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Mar. 10, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Jin Ha Kim, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/16 (2023.01); H01L 27/01 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/162 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/016 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80031 (2013.01); H01L 2224/80039 (2013.01); H01L 2224/80048 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/30101 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.


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