The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Nov. 13, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyo-Sub Kim, Seoul, KR;

Sohyun Park, Seoul, KR;

Daewon Kim, Seoul, KR;

Dongoh Kim, Daegu, KR;

Eun A Kim, Seoul, KR;

Chulkwon Park, Hwaseong-si, KR;

Taejin Park, Yongin-si, KR;

Kiseok Lee, Hwaseong-si, KR;

Sunghee Han, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 27/108 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/7682 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/5329 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10888 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01);
Abstract

A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.


Find Patent Forward Citations

Loading…