Page buffer circuits and nonvolatile memory devices including the same

Abstract

A nonvolatile memory device includes a memory cell array including memory cells and a page buffer circuit. The page buffer circuit includes page buffer units and cache latches. The cache latches are spaced apart from the page buffer units in a first horizontal direction, and correspond to respective ones of the plurality of page buffer units. Each of the page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal. The page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units, from a first portion of cache latches to a data input/output (I/O) line, the data transfer operation configured to dump sensed data from a second portion of page buffer units to a second portion of cache latches.