The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Oct. 08, 2021
Applicant:

Honeywell International Inc., Charlotte, NC (US);

Inventor:

Keith Golke, Minneapolis, MN (US);

Assignee:

Honeywell International Inc., Charlotte, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4094 (2006.01); G11C 17/12 (2006.01); G11C 11/4074 (2006.01); G11C 11/4099 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 11/4074 (2013.01); G11C 11/4099 (2013.01); G11C 17/126 (2013.01);
Abstract

An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.


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