The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

May. 18, 2017
Applicants:

Nec Corporation, Tokyo, JP;

Bar-ilan University, Ramat Gan, IL;

Inventors:

Toshinori Araki, Tokyo, JP;

Kazuma Ohara, Tokyo, JP;

Jun Furukawa, Herzliya, JP;

Lindell Yehuda, Ramat Gan, IL;

Nof Ariel, Ramat Gan, IL;

Assignees:

NEC CORPORATION, Tokyo, JP;

BAR-ILAN UNIVERSITY, Ramat Gan, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/78 (2013.01); G06F 7/501 (2006.01); G06F 21/82 (2013.01); H04L 9/08 (2006.01); G06F 7/72 (2006.01); H04L 9/00 (2022.01); H04L 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 21/78 (2013.01); G06F 7/501 (2013.01); G06F 7/727 (2013.01); G06F 21/82 (2013.01); H04L 9/08 (2013.01); H04L 9/002 (2013.01); H04L 9/3026 (2013.01);
Abstract

The present invention provides a bit decomposition secure computation system comprising: a share value storage apparatus to store share values obtained by applying (2, 3) type RSS using modulo of power of 2 arithmetic; a decomposed share value storage apparatus to store a sequence of share values obtained by applying (2, 3) type RSS using modulo 2 arithmetic; and a bit decomposition secure computation apparatus that, with respect to sharing of a value w, r1, r2, and r3 satisfying w=r1+r2+r3 mod 2{circumflex over ( )}n, where {circumflex over ( )} is a power operator and n is a preset positive integer, being used as share information by the (2, 3) type RSS stored in the share value storage apparatus, includes: an addition sharing unit that sums two values out of r1, r2 and r3 by modulo 2{circumflex over ( )}n, generates and distributes a share value of the (2, 3) type RSS with respect to the sum; and a full adder secure computation unit that executes addition processing of the value generated by the addition sharing unit and a value not used by the addition sharing unit, for each digit, by using secure computation of a full adder, and stores the result in the decomposed share value storage apparatus.


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