The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

May. 08, 2020
Applicant:

Ares Technologies, Inc., Boston, MA (US);

Inventors:

Christian T Wentz, Providence, RI (US);

Ilia Lebedev, Cambridge, MA (US);

Assignee:

Ares Technologies, Inc., Boston, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/71 (2013.01); H04L 9/32 (2006.01); G05B 19/418 (2006.01); G06F 30/398 (2020.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01); G01R 31/26 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G05B 19/41875 (2013.01); G01R 31/26 (2013.01); G01R 31/317 (2013.01); G01R 31/318342 (2013.01); G06F 21/71 (2013.01); G06F 30/398 (2020.01); H04L 9/3236 (2013.01); G06F 2119/18 (2020.01);
Abstract

A method for testing circuit elements at one or more manufacturing stages comprising receiving, at a circuit verifier a fingerprint of at least a circuit element to be manufactured, wherein the fingerprint further comprises at least an expected output corresponding to at least a test input, transmitting, from the circuit verifier the at least a test input to the at least a circuit element, receiving, at the circuit verifier at least a test output from the at least a circuit element, and comparing, by the circuit verifier the at least a test output to the at least an expected output of the fingerprint of the at least a circuit element.


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