The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2023
Filed:
Aug. 13, 2021
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Raghu Ganesan, Bengaluru, IN;
Saravanakkumar Radhakrishnan, Aruppukottai, IN;
Gaurav Aggarwal, Rohini Delhi, IN;
Rallabandi V Lakshmi Annapurna, Bengaluru, IN;
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/04 (2006.01); H04L 25/03 (2006.01); H04L 25/02 (2006.01); H04B 1/30 (2006.01);
U.S. Cl.
CPC ...
H04B 1/04 (2013.01); H04L 25/0202 (2013.01); H04L 25/03961 (2013.01); H04B 2001/045 (2013.01); H04B 2001/0441 (2013.01); H04B 2001/305 (2013.01);
Abstract
A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.