The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2023
Filed:
Mar. 23, 2018
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Tadashi Iijima, Kanagawa, JP;
Takatoshi Kameshima, Kanagawa, JP;
Ikue Mitsuhashi, Kanagawa, JP;
Hiroshi Horikoshi, Tokyo, JP;
Hideto Hashiguchi, Kanagawa, JP;
Reijiroh Shohji, Tokyo, JP;
Minoru Ishida, Tokyo, JP;
Masaki Haneda, Kanagawa, JP;
SONY GROUP CORPORATION, Tokyo, JP;
Abstract
A solid-state imaging device includes first through third substrates. The first substrate includes a first semiconductor substrate and a first multi-layered wiring layer stacked thereon. The second substrate includes a second semiconductor substrate and a second multi-layered wiring layer stacked thereon. The third substrate includes a third semiconductor substrate and a third multi-layered wiring layer stacked thereon. A coupling structure for electrically coupling at least two of the first through third substrates includes a via. The via exposes a predetermined wiring line in the second multi-layered wiring layer while exposing a portion of a predetermined wiring line in the first multi-layered wiring layer from a back surface side of the first substrate, or exposes a predetermined wiring line in the third multi-layered wiring layer while exposing a portion of the predetermined wiring line in the first multi-layered wiring layer or the second multi-layered wiring layer from the back surface.