The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

Feb. 23, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Masaru Koyanagi, Ota Tokyo, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H01L 27/11551 (2017.01); H01L 27/11578 (2017.01); H01L 21/768 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 25/07 (2006.01); H01L 25/11 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/105 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H01L 25/071 (2013.01); H01L 25/074 (2013.01); H01L 25/112 (2013.01); H01L 25/117 (2013.01); H01L 27/0694 (2013.01); H01L 27/2481 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.


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