Display device improving response speed of a gate clock signal or eliminating delay in the gate clock signal

Abstract

A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.