The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

Mar. 05, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Paolo Di Febbo, Cupertino, CA (US);

Waleed Abdulla, Cupertino, CA (US);

Chaminda N. Vidanagamachchi, Cupertino, CA (US);

Yohan Rajan, Cupertino, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06N 3/08 (2023.01); G06N 3/04 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01);
Abstract

Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.


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