The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

Dec. 28, 2018
Applicant:

Maxlinear, Inc., Carlsbad, CA (US);

Inventors:

Jiaxiang Shi, Singapore, SG;

Chun Feng Hu, Singapore, SG;

Yao Chye Lee, Singapore, SG;

Qiming Wu, Singapore, SG;

Assignee:

MaxLinear, Inc., Carlsbad, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/57 (2013.01); G11C 29/38 (2006.01); G06F 9/4401 (2018.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/575 (2013.01); G06F 3/0604 (2013.01); G06F 3/0622 (2013.01); G06F 3/0659 (2013.01); G06F 9/4401 (2013.01); G11C 29/38 (2013.01); G06F 2221/034 (2013.01);
Abstract

A boot read only memory (ROM) chip unit can perform a secure boot routine based on various operations. A processor device comprises a boot ROM chip with processing circuitry on a system board configured to perform a system board power up according to a read operation in a one-time-programmable OTP memory/non-volatile memory (NVM). The OTP memory/NVM includes a spare area in a portion of the OTP/NVM that can receive a first sequence pattern. The processor determines whether a secure boot indication indicates a secure boot routine, and differentiates one or more read return content of the OTP memory/NVM between a wrongly read return content and a trusted read return content, in response to, or concurrent with, the secure boot indication indicating the secure boot routine.


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