The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

May. 12, 2021
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Dany Davidov, Tirat Carmel, IL;

Misbah Ramadan, Haifa, IL;

Itamar Rozen, Givat Ela, IL;

Tzach Zemer, Megadim, IL;

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3203 (2019.01); G06F 1/18 (2006.01); G06F 13/36 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3203 (2013.01); G06F 1/18 (2013.01); G06F 13/36 (2013.01); G06F 13/4022 (2013.01);
Abstract

A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.


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