The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

Apr. 22, 2016
Applicant:

Suteng Innovation Technology Co., Ltd, Shenzhen, CN;

Inventors:

Chunxin Qiu, Shenzhen, CN;

Letian Liu, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 17/08 (2006.01); G01S 7/484 (2006.01); G01S 7/487 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
G01S 17/08 (2013.01); G01S 7/484 (2013.01); G01S 7/487 (2013.01); H03M 1/12 (2013.01);
Abstract

Provided are a pulse laser ranging system and method employing a time domain waveform matching technique. The system comprises a software part and a hardware part. The hardware part comprises an optical collimation system, an FPGA, a filter, a photoelectric conversion system, an analog amplifier circuit, a laser transmitter, a signal combination system, an ADC sampling system and a narrow pulse laser transmitting circuit. When transmitting a control signal to control laser transmission, the FPGA sends a time reference pulse to the signal combination system. The signal combination system integrates the time reference pulse with a fixed amplitude analog echo signal to form an echo signal with a time reference. The echo signal with a time reference is quantified into a digital detection signal in the ADC sampling system. The digital detection signal is sent to the FPGA to undergo data analysis. The software part is used to perform time domain waveform matching analysis to obtain a ranging result. The ranging result is output by the FPGA.


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