Floating point to fixed point conversion using exponent offset

Abstract

A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes an offset unit configured to offset the exponent of the floating point number by an offset value equal to (iw−1−s) to generate a shift value sof sw bits given by s=(B−E)+(iw−1−s), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format; a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the shifter being configured to right-shift the input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2−1, iw−1−s)+min(2−2, fw)]≤k≤sw, where s=1 for a signed floating point number and s=0 for an unsigned floating point number.