logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11587941 B1

PDFFull Text
Date of Patent:
Feb. 21, 2023

Filed:

Apr. 16, 2020

Method of planarizing insulating layer for memory device

Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Byung Woo Kang, Incheon, KR;

Sae Jun Kwon, Seoul, KR;

Hwal Pyo Kim, Suwon-si, KR;

Jin Taek Park, Suwon-si, KR;

Yang Seok Lim, Icheon-si, KR;

Young Ock Hong, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:

William Park & Associates Ltd.

Primary Examiner:

Davienne N Monbleau

Assistant Examiner:

Nader M Elmarhoumi

Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 21/822 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/76224 (2013.01); H01L 21/76227 (2013.01); H01L 21/76229 (2013.01); H01L 21/822 (2013.01); H01L 21/823481 (2013.01); H01L 27/11582 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.

Find Patent Forward Citations

Kang, Byung. (2023). Method of planarizing insulating layer for memory device (U.S. Patent No. 11587941). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11587941

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…