The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Oct. 28, 2020
Applicant:

Silicon Space Technology Corporation, Austin, TX (US);

Inventors:

David R. Gifford, Pflugerville, TX (US);

Patrice M. Parris, Phoenix, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/74 (2006.01); H01L 29/10 (2006.01); H01L 27/092 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 21/743 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/76237 (2013.01); H01L 21/823892 (2013.01); H01L 27/0921 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/1083 (2013.01); H01L 29/1087 (2013.01); H01L 21/76202 (2013.01); H01L 21/823878 (2013.01);
Abstract

Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.


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