The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Apr. 29, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Steven R. Carlough, Poughkeepsie, NY (US);

Susan M. Eickhoff, Hopewell Junction, NY (US);

Warren E. Maule, Cedar Park, TX (US);

Patrick J. Meaney, Poughkeepsie, NY (US);

Stephen J. Powell, Austin, TX (US);

Gary A. Van Huben, Poughkeepsie, NY (US);

Jie Zheng, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 7/10 (2006.01); G06F 3/06 (2006.01); G11C 5/04 (2006.01); G06F 12/08 (2016.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/109 (2013.01); G06F 3/0611 (2013.01); G06F 3/0626 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0685 (2013.01); G06F 12/08 (2013.01); G11C 5/04 (2013.01); G11C 7/1003 (2013.01); G11C 7/1078 (2013.01); G11C 7/22 (2013.01); G11C 2207/2245 (2013.01);
Abstract

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.


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