The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Feb. 05, 2020
Applicant:

Alibaba Group Holding Limited, Grand Cayman, KY;

Inventors:

Zhibin Xiao, San Mateo, CA (US);

Xiaoxin Fan, San Mateo, CA (US);

Minghai Qin, San Mateo, CA (US);

Assignee:

Alibaba Group Holding Limited, Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 16/22 (2019.01); G06N 3/02 (2006.01); G06F 16/174 (2019.01); G06F 9/30 (2018.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 16/2237 (2019.01); G06F 9/30018 (2013.01); G06F 16/1744 (2019.01); G06F 17/16 (2013.01); G06N 3/02 (2013.01);
Abstract

The present disclosure relates to a method and an apparatus for representation of a sparse matrix in a neural network. In some embodiments, an exemplary operation unit includes a buffer for storing a representation of a sparse matrix in a neural network, a sparse engine communicatively coupled with the buffer, and a processing array communicatively coupled with the sparse engine. The sparse engine includes circuitry to: read the representation of the sparse matrix from the buffer, the representation comprising a first level bitmap, a second level bitmap, and an element array; decompress the first level bitmap to determine whether a block of the sparse matrix comprises a non-zero element; and in response to the block comprising a non-zero element, decompress the second level bitmap using the element array to obtain the block of the sparse matrix. The processing array includes circuitry to execute the neural network with the sparse matrix.


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