The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Dec. 13, 2019
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Weon Taek Na, Bellevue, WA (US);

Jagadish B. Kotra, Austin, TX (US);

Yasuko Eckert, Bellevue, WA (US);

Steven Raasch, Boxborough, MA (US);

Sergey Blagodurov, Bellevue, WA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/0871 (2016.01); G06F 9/30 (2018.01); G06F 12/0882 (2016.01); G06F 12/1027 (2016.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/30036 (2013.01); G06F 12/0831 (2013.01); G06F 12/0871 (2013.01); G06F 12/0882 (2013.01); G06F 12/1027 (2013.01);
Abstract

A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.


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