The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Sep. 17, 2020
Applicant:

United States of America As Represented BY the Administrator of Nasa, Washington, DC (US);

Inventors:

Alessandro Geist, Bethesda, MD (US);

Cody Brewer, Greenbelt, MD (US);

Robin A. Ripley, Greenbelt, MD (US);

Christopher M. Wilson, Greenbelt, MD (US);

Nicholas Franconi, Greenbelt, MD (US);

Gary A. Crum, Silver Spring, MD (US);

David J. Petrick, Severna Park, MD (US);

Thomas P. Flatley, Huntingtown, MD (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 30/34 (2020.01); H03M 13/19 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/106 (2013.01); G06F 11/1629 (2013.01); G06F 30/34 (2020.01); H03M 13/19 (2013.01);
Abstract

The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.


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