The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Nov. 01, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Fadi Y. Busaba, Poughkeepsie, NY (US);

Harold W. Cain, III, Raleigh, NC (US);

Michael Karl Gschwind, Chappaqua, NY (US);

Valentina Salapura, Chappaqua, NY (US);

Timothy J. Slegel, Staatsburg, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/46 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 3/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0817 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 9/467 (2013.01); G06F 3/061 (2013.01); G06F 3/0605 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/0811 (2013.01); G06F 12/0828 (2013.01); G06F 12/0862 (2013.01); G06F 13/16 (2013.01); G06F 13/42 (2013.01); G06F 2212/283 (2013.01); G06F 2212/602 (2013.01); G06F 2212/621 (2013.01);
Abstract

A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.


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