The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2023
Filed:
Nov. 27, 2019
Applicant:
Arm Limited, Cambridge, GB;
Inventors:
Shardendu Shekhar, Austin, TX (US);
Andy Wangkun Chen, Austin, TX (US);
Anil Kumar Baratam, Bangalore, IN;
James Dennis Dodrill, Dripping Springs, TX (US);
Yew Keong Chong, Austin, TX (US);
Assignee:
Arm Limited, Cambridge, GB;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 7/53 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3869 (2013.01); G06F 7/5324 (2013.01); G06F 7/5443 (2013.01); G06F 9/30014 (2013.01); G06F 9/30032 (2013.01); G06F 9/3893 (2013.01); G06F 12/0207 (2013.01);
Abstract
Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.