The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Dec. 15, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Robert Matthew Mertens, Austin, TX (US);

Ateet Omer, Uttar Pradesh, IN;

Sanjay Kumar Wadhwa, Uttar Pradesh, IN;

Charles Eric Seaberg, Austin, TX (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); H03K 21/08 (2006.01); H03M 7/16 (2006.01); H03K 5/01 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/04 (2013.01); H03K 5/01 (2013.01); H03K 21/08 (2013.01); H03M 7/165 (2013.01); H03K 2005/00078 (2013.01);
Abstract

A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.


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