The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Jul. 16, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Subhashish Mukherjee, Bangalore, IN;

Jayawardan Janardhanan, Bangalore, IN;

Yogesh Darwhekar, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); G04F 10/00 (2006.01); H03K 5/135 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1033 (2013.01); G04F 10/005 (2013.01); H03K 5/135 (2013.01); H03K 2005/00052 (2013.01);
Abstract

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.


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