The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Mar. 10, 2022
Applicant:

Hirose Electric Co., Ltd., Kanagawa, JP;

Inventors:

Ching-Chao Huang, San Jose, CA (US);

Jeremy Buan, San Jose, CA (US);

Jingqian Tian, San Jose, CA (US);

Tadashi Ohshida, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/12 (2006.01); H03K 5/1252 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); H03K 2005/00078 (2013.01);
Abstract

A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.


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