The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Aug. 18, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Sarosh I. Azad, Fremont, CA (US);

Benson Chau, Sunnyvale, CA (US);

Tomai Knopp, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/02 (2006.01); H03K 23/60 (2006.01); H03K 19/20 (2006.01); H03K 19/173 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/023 (2013.01); H03K 19/1737 (2013.01); H03K 19/20 (2013.01); H03K 23/60 (2013.01); H03K 2005/00286 (2013.01);
Abstract

An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.


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