The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2023
Filed:
Apr. 29, 2021
Cypress Semiconductor Corporation, San Jose, CA (US);
David Michael Rogers, Sunnyvale, CA (US);
Henry H. Yuan, San Ramon, CA (US);
Mimi Qian, Campbell, CA (US);
Myeongseok Lee, Campbell, CA (US);
Sungkwon Lee, Saratoga, CA (US);
Yan Yi, Mountain View, CA (US);
Ravindra M. Kapre, San Jose, CA (US);
Murtuza Lilamwala, San Jose, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.